Difference between revisions of "Hardware Protection"
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[[Hardware Protection]] offered by Hardware Security Modules (HSM see [[FIPS 140]]) or management chips. | [[Hardware Protection]] offered by Hardware Security Modules (HSM see [[FIPS 140]]) or management chips. | ||
==Context== | ==Context== | ||
| − | * On 2020-11-17 | + | * On 2020-11-17 <ref>Lily Hay Newman ''Microsoft Is Making a Secure PC Chip—With Intel and AMD's Help''. (2020-11-17) Wired https://www.wired.com/story/microsoft-pluton-secure-processor<lref> Microsoft announced that they planned to enable the Pluton design on chips from Intel and AMD. |
* Both Intel and ARM enable secure enclaves on their Microprocessor to protect security. | * Both Intel and ARM enable secure enclaves on their Microprocessor to protect security. | ||
* Latest version as of 2019-05-22 is [https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.140-3.pdf FIPS 140-3], version 3. | * Latest version as of 2019-05-22 is [https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.140-3.pdf FIPS 140-3], version 3. | ||
Revision as of 18:00, 25 November 2020
Full Title
Hardware Protection offered by Hardware Security Modules (HSM see FIPS 140) or management chips.
Context
- On 2020-11-17 Cite error: Closing
</ref>missing for<ref>tag
References
Other Material
- See wiki page Smart Phone for a discussion of hardware versus software protection within a modern ARM based Trusted Execution Environment.
